This invention relates to microelectronic devices and fabrication methods therefor, and more particularly to light emitting devices, such as light emitting diodes (LEDs) and manufacturing methods therefor.
Light emitting diodes are widely used in consumer and commercial applications. As is well known to those having skill in the art, a light emitting diode generally includes a diode region on a microelectronic substrate. The microelectronic substrate may comprise, for example, gallium arsenide, gallium phosphide, alloys thereof, silicon carbide and/or sapphire. Continued developments in LEDs have resulted in highly efficient and mechanically robust light sources that can cover the visible spectrum and beyond. These attributes, coupled with the potentially long service life of solid state devices, may enable a variety of new display applications, and may place LEDs in a position to compete with the well entrenched incandescent and fluorescent lamps.
Gallium Nitride (GaN)-based LEDs typically comprise an insulating or semiconducting substrate such as silicon carbide (SiC) or sapphire on which a plurality of GaN-based epitaxial layers are deposited. The epitaxial layers comprise an active or diode region having a p-n junction which emits light when energized.
LEDs may be mounted substrate side down onto a submount, also called a package or lead frame (hereinafter referred to as a xe2x80x9csubmountxe2x80x9d). In contrast, flip-chip mounting of light emitting diodes involves mounting the LED onto the submount with the substrate side facing up (i.e. away from the submount). Light may be extracted and emitted through the substrate. Flip chip mounting may be an especially desirable technique for mounting SiC-based LEDs. In particular, since SiC has a higher index of refraction than GaN, light generated in the active or diode region generally does not totally internally reflect (i.e. reflect back into the GaN-based layers) at the GaN/SiC interface. Flip chip mounting of SiC-based LEDs also can improve the effect of certain substrate-shaping techniques known in the art. Flip chip packaging of SiC LEDs may have other benefits, such as improved heat dissipation, which may be desirable depending on the particular application for the LED.
Because of the high index of refraction of SiC, light passing through an SiC substrate tends to be totally internally reflected into the substrate at the surface of the substrate unless the light strikes the surface at a fairly low angle of incidence (i.e. fairly close to normal). The critical angle for total internal reflection generally depends on the material with which SiC forms an interface. It is possible to increase the light output from an SiC-based LED by shaping the SiC substrate in a manner that limits total internal reflection by causing more rays to strike the surface of the SiC at low angles of incidence. A number of such shaping techniques and resulting devices are taught in the above-cited U.S. patent application Ser. No. 10/057,821.
One potential problem with flip-chip mounting is that when an LED is mounted on a submount using conventional techniques, a conductive die attach material such as silver epoxy is deposited on the LED and/or on the package, and the LED and the submount are pressed together. This can cause the viscous conductive die attach material to squeeze out and make contact with the N-type substrate and/or layers in the device, thereby forming a Schottky diode connection that can short-circuit the p-n junction in the active region.
Metal-metal bonds formed by soldering, thermosonic scrubbing and/or thermocompression bonding are alternative attach techniques. However, tin (Sn) is a component of most types of solder, and migration of Sn from the bonded surface into the device can cause unwanted degradation of the device. Such migration can interfere with metal-semiconductor interfaces such as ohmic contacts and/or the function of metalxe2x80x94metal interfaces such as reflective interfaces that serve as mirrors.
Light emitting diodes according to some embodiments of the present invention include a substrate, an epitaxial region on the substrate that includes therein a diode region, and a multilayer conductive stack including a barrier layer on the epitaxial region opposite the substrate. A passivation layer extends at least partially on the multilayer conductive stack opposite the epitaxial region, to define a bonding region on the multilayer conductive stack opposite the epitaxial region. The passivation layer also extends across the multilayer conductive stack, across the epitaxial region and onto the substrate.
In some embodiments of the present invention, the passivation layer is non-wettable to a bonding material that is used to attach the bonding region to a submount. In other embodiments of the present invention, the multilayer conductive stack and the epitaxial region both include a sidewall, and the passivation layer extends on the sidewalls of the multilayer conductive stack and the epitaxial region. In still other embodiments of the present invention, a bonding layer is provided on the bonding region. In some embodiments of the present invention, the bonding layer includes a sidewall and the passivation layer also extends onto the sidewall of the bonding layer. In yet other embodiments, the passivation layer does not extend on the bonding layer sidewall. In still other embodiments of the present invention, an adhesion layer and/or a solder wetting layer are provided between the multilayer conductive stack and the bonding layer. In yet other embodiments of the present invention, the adhesion layer includes an adhesion layer sidewall and the passivation layer also extends on the adhesion layer sidewall. In still other embodiments, the passivation layer does not extend on the adhesion layer sidewall.
In still other embodiments of the present invention, the substrate includes a first face adjacent the epitaxial region and a second face opposite the epitaxial region. In some embodiments of the present invention, the bonding layer has smaller surface area than the multilayer conductive stack, the multilayer conductive stack has smaller surface area than the epitaxial region and the epitaxial region has smaller surface area than the first face. In other embodiments of the present invention, the second face also has smaller surface area than the first face.
Still other embodiments of the present invention include a submount and a bond between the bonding region and the submount. In some embodiments of the present invention, the bond is a thermocompression bond. In other embodiments of the present invention, the bond comprises solder.
Light emitting diodes according to other embodiments of the present invention include a substrate having first and second opposing faces, the second face having smaller surface area than the first face. An epitaxial region is provided on the first face that includes therein a diode region. An ohmic layer is on the epitaxial region opposite the substrate. A reflector layer is on the ohmic layer opposite the epitaxial region. A barrier layer is on the reflector layer opposite the ohmic layer. An adhesion layer is on the barrier layer opposite the reflector layer. A bonding layer is on the adhesion layer opposite the barrier layer. In other embodiments, a solder wetting layer is on the adhesion layer opposite the barrier layer. Other embodiments of the present invention further comprise a submount and a bond between the bonding layer and the submount.
In some embodiments of the present invention, the ohmic layer comprises platinum, palladium, nickel/gold, nickel oxide/gold, nickel oxide/platinum, titanium and/or titanium/gold. In still other embodiments of the present invention, the reflector layer comprises aluminum and/or silver. In some embodiments of the present invention, the barrier layer comprises tungsten, titanium/tungsten and/or titanium nitride/tungsten. In other embodiments of the present invention, the barrier layer comprises a first layer comprising tungsten, and a second layer comprising nickel on the first layer. In some embodiments of the present invention, the solder has a reflow temperature of less than about 210xc2x0 C., and the barrier layer comprises a layer of titanium/tungsten that is between about 500 xc3x85 thick and about 50,000 xc3x85 thick. In other embodiments of the present invention, the solder has a reflow temperature of more than about 210xc2x0 C. and the barrier layer comprises a first layer of titanium/tungsten that is about 5000 xc3x85 thick, and a second layer comprising nickel that is about 2000 xc3x85 thick, on the first layer. In still other embodiments of the present invention, the solder has a reflow temperature of more than about 250xc2x0 C. and the barrier layer comprises a first layer of titanium/tungsten that is about 5000 xc3x85 thick and a second layer comprising nickel that is about 2000 xc3x85 thick, on the first layer.
In other embodiments of the present invention, the epitaxial region has smaller surface area than the second face. The barrier layer, the reflector layer and the ohmic layer have same surface area which is less than that of the epitaxial region. The adhesion layer and the bonding layer have same surface area that is smaller than that of the barrier layer, the reflective layer and the ohmic layer. In still other embodiments of the present invention, a passivation layer as was described above also may be provided.
Passivation layers according to some embodiments of the present invention provide means for preventing an external short circuit across the epitaxial region. Moreover, a barrier layer comprising a tungsten, titanium/tungsten and/or titanium nitride/tungsten layer or titanium/tungsten and nickel layers according to some embodiments of the present invention provide means for reducing migration of tin and/or other potentially deleterious materials into the multilayer conductive stack.
Light emitting diodes may be fabricated, according to some embodiments of the present invention, by epitaxially forming a plurality of spaced apart mesa regions on a substrate, wherein the mesa regions include therein a diode region. First reduced area regions are defined on the mesa regions, for example using photolithography. A multilayer conductive stack that includes a barrier layer is formed on the first reduced area regions of the mesa regions. A passivation layer is formed on the substrate between the mesa regions, on exposed portions of the mesa regions and on exposed portions of the multilayer conductive stacks. The barrier layer defines second reduced area regions on the multilayer conductive stacks. A bonding layer is formed on the second reduced area regions of the multilayer conductive stacks. The substrate is then diced between the mesas, to produce a plurality of light emitting diodes. In other embodiments of the present invention, the dicing is followed by bonding the bonding layer to a submount. In some embodiments of the present invention, thermocompression bonding is used. In other embodiments of the present invention, solder bonding is used.